4th Internal Conference on Computer Architecture (ICCA'03)
Anf. A2, Dep. Inf.,
Univ. Minho
Campus Gualtar, Braga, PORTUGAL
Editor: Alberto
José Proença (Editor's
Message)
Conference Proceedings
Last update: 14-Feb-03
Programme
*********** 31-Jan-03 **********
9h00 Session
1
64-bit CPU's
11h00 Session
2
Performance Analysis & Evaluation
14:30 Session
3
Smart Cards and Novel Processor Approaches
16:20 Session
4
Embedded Systems
*********** 01-Fev-03 **********
09:00 Session
5
Application Specific Processors
10:50 Session
6
Parallel and Distributed Environments
Instructions for authors
Chairman: Alberto José Proença
09h00m Welcome Session
Alberto José Proença09h20m Minimizing Errors in FP Arithmetic (paper,sorry, no communication)
Cristiana Manuela Guimarães de Freitas
Abstract. Using finite systems to represent non-finite quantities may lead to serious hazards in real life. Some of these are here presented together with a short explanation. Manufacturers of 64-bit CPUs are developing newer approaches to reduce these negative factors, from increasing bit representation to interval arithmetic computation; an overview of two of these approaches - from Intel and Sun - are here analysed.
Ref. "What Every Computer Scientist Should Know About Floating-Point Arithmetic"
"Instructor Manual for Computer Hardware and Algorithms"
"IA-64 Floating-Point Operations and the IEEE Standard for Binary Floating-Point Arithmetic"
"Interval Arithmetic in High Performance Technical Computing"09h40m UltraSparc-III vs. Intel IA-64 (paper, slides)
Maria Celeste Marques Pinto
Abstract. This communication sets an evaluation framework and performs a comparative analysis of the UltraSPARC-III and the IA-64 processor architectures. It starts with an overview of a pure RISC architecture and the new EPIC technology. It then presents the unique combination of innovative features that both manufacturers claim - explicit parallelism, predication and speculative loading – and the goals for their architecture design: to be highly scalable to fill the ever-increasing performance requirements of various server and workstation market segments.
Ref. "UltraSPARC-III: Designing Third-Generation 64-Bit Performance"10h00m AMD Hammer vs.Intel IA-64 (paper, slides)
Rui Augusto de Campos Martins
Abstract. The AMD Hammer processor architecture is designed to provide a migration path from IA-32 to 64-bit applications. This communication presents an overview of its architecture, stressing the integrated memory controller and the high-speed scalable system bus, aiming a high performance multi-way processing solution. It also shows some implementations differences between the Hammer and the Itanium processors, namely in their 32-bit backwards compatibilities,and on their performance ratings.
Ref. "A Glance at the Future: AMD Hammer Processors and x86-64 Technology"10h20m IBM POWER4: a 64-bit Architecture and a new Technology to form Systems (paper, slides)
Rui Daniel Gomes de Macedo Fernandes
Abstract. The IBM POWER4, a new 64-bit architecture for the POWER family, includes now Symmetric MultiProcessing capabilities (SMP), referred as a distributed switch. In this communication we take a closer look into its main features and microarchitecture improvements and we will try to place its position on the high-end servers.
Ref. "POWER4 system microarchitecture"
"Power4 Focuses on Memory Bandwidth"
10h40m Coffee break
Session 2
Performance Analysis & Evaluation
Chairman: João Luís Sobral
11h00m Speed-up Techniques in Matrix Computation: a Case Study (paper, slides)
Paula Alexandra Fernandes Monteiro
José Jorge Abrantes Coelho Moura
Abstract. Improvements on the execution performance of a given application can be obtained simply by the use of more efficient algorithms, a better codification and by the selection of adequate compilation options. The present study aims to analyse these different scopes, and to apply this methodology to square matrix multiplication. The case study uses C language, the GCC compiler, and a reference algorithm taken from the BLAS library. This study also aims to examine the assembly code generated and comment the impact the codification and compilation techniques have on the whole process.
Ref. Matrix Computation ...11h40m Profiling Techniques for Load Distribution in Distributed Systems (sorry, no communication)
Paulo Jorge Martinho Coto
Abstract. To distribute the computing and data load of a heavy application running in a parallel environment on a shared distributed system, up-dated data on the computing capacity and communication availability from each node, is required for the decision making process. An analysis of some current techniques to perform these measurement tasks precedes the presentation of some measured results on a real environment, and some hints are also presented to apply the methodology to other applications.
Ref. "Capacity and Performance Analysis of Distributed Enterprise Systems"
Cluster Computing ...12h00m An Economic Contribution to solve Load Distribution Problems (paper, slides)
Joel Alexandre da Silva Vicente
Abstract. Due to the similarity found between an economy and a distributed computer system, microeconomics concepts and algorithms were introduced to bring a new approach to the traditional distributed workload that is inefficient in modern complex distributed systems. This new approach defines a distributed computer system as an economy where competition sets prices for the resources in the system. Jobs compete for these resources by issuing bids, and the resource allocation decisions are made through auctions held by processors. In this way, competition and a price system limits the complexity of the allocation resources process.
Ref. "Economic Models for Allocating Resources in Computer Systems"
"AN OPPORTUNITY COST APPROACH FOR JOB ASSIGNMENT IN A SCALABLE COMPUTING CLUSTER"
"A COST-BENEFIT FRAMEWORK FOR ONLINE MANAGEMENT OF A METACOMPUTING SYSTEM"
12h30m Lunch
Session 3
Smart Cards and Novel Processor Approaches
Chairman: António Manuel Pina
14h30m Smart Card Evolution (paper, slides)
Fernando Jorge Ramos Ferreira
Abstract. This communication describes the state of art in smart-card technology and explores some of the consumer applications currently in use. Smart cards are powerful devices that can be programmed to perform a number of security-related tasks, ranging from user identification to secured network transmissions. New Java and PC/SC smart cards coupled to biometrics provide almost unlimited potential for PC applications. With operating systems providing native support, smart-card technology will be positioned in a mainstream computer industry tool.
Ref. "Smart Card Evolution"14h50m BioSmartcards: the Key to securely bind you personal ID (sorry, no communication)
José Carlos do Carmo Carvalho
Abstract. Smartcards become a technological environment on secure human-computer interface solutions. This need of combining a mobile hardware device with individual human features evolved into a single piece known as BioSmartcards. This communication describes the main features of both worlds, the challenges on merging them into an sigle chip, and also addresses the main security problems and expectations from this thecnology.
Ref. "Biometrics as the Key to your Smartcard"15h10m Raw: Microprocessor for Extroverted Computing Support (paper, slides)
Nuno Alexandre Magalhães Pereira
Abstract. A simple, highly parallel, VLSI architecture that exposes the hardware details to the compiler is proposed has the base platform to empower the emergence of pervasive, human centred computing experience. This communication discloses the motivation to build such architecture, analyses its details, presents its relationship to past and present architectures, and closes by addressing issues on compiling techniques, which enable an efficient use of silicon area and I/O pins.
Ref. "THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL-PURPOSE PROGRAMS"15h30m Multithreaded Architectures (paper, slides)
Filipe José Silva de Campos
Abstract. The increasing gap between CPU and memory speed are driving several optimizations to be used in the architecture of the most recent processor, such as the HyperTreading technology. This comunication explores this technology, and also attempts to draw some conclusion about its real value.
Ref. "Media Applications on Hyper-Threading Technology"
"A multithreaded PowerPC processor for commercial servers"
"Speculative Multithreaded Processors"
"Instruction-Level Distributed Processing"16h00m Coffee break
Chairman: João Miguel Fernandes
16h20m Wearable Computing: the Present and the Future (paper, slides)
Ana Maria Martins Henriques
Abstract. The concept of wearable computing is a natural reaction for the everyday people's needs. It requires a description of the interface that gives physical senses, communication, intellect and abstraction capacity from the user's point of view. This communication resumes the wearable designer's needs as they balance power requirements and network resources, presenting the possibilities wearable systems can offer.
Ref. "THE CHALLENGES OF WEARABLE COMPUTING. Part1 Part2"
"Adding Some smartness to Devices and Everyday Things"16h40m Smart Cameras as Embedded Systems (paper, slides)
António Manuel Ribeiro de Sousa
Abstract. A "smart camera" is basically a video camera coupled to a computer vision system in a tiny package. This communication begins stating the main differences between smart cameras and standard smart vision systems. A smart camera architecture is described whereby a combination of an on-board microprocessor and PLD’s allow for the embedding of image processing algorithms in the camera. A static thresholding algorithm is presented which demonstrates the ability to track non-uniformity in the inspection target. A multi camera inspection system application is presented where a maximum of twenty smart cameras may be networked together to a single host computer. Finally, a prediction is made of technological and applicational future evolution on smart cameras.
Ref. "Smart Cameras as Embedded Systems"17h00m A Simple Architecture for Embbeded Web Servers (paper, slides)
Luís Miguel Alves Domingues
Abstract. Older technologies can still play an important role in embedded systems. Complex applications such as a Web server can be embedded implemented, with some restrictions and assumptions, and still be efficient for current industry demands. This communication makes an incursion into the hardware architecture behind an embedded Web server based on simple 8051-type processors. It presents and discusses architectural features, limitations, performance and trends.
Ref. "Build Your Own 8051 Web Server"
"MSP430 Internet Connectivity"17h20m Networks on Chips (NOC): Design Challenges (paper, slides)
Maria Elizabete Marques Duarte
Abstract. With the growth of the number of SOC components it is necessary to revalue the design technology and architecture. This work overviews the field of Networks on Chip (NOC), and addresses the distinguishing features of the several architectural designs of a NOC (Octagon and Eclipse). The limitations of the interconnect technology are discussed as well as how his technology has been scaled down to meet systems requirements.
Ref. "Networks on Chips: A New SoC Paradigm"
"AN INTERCONNECT ARCHITECTURE FOR NETWORKING SYSTEMS ON CHIPS"
"A SCALABLE HIGH-PERFORMANCE COMPUTING SOLUTION FOR NETWORKS ON CHIPS"
"Available Instruction- Level Parallelism for Superscalar and Superpipelined Machines"
"Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading"
"In Search of Speculative Thread-Level Parallelism"
"Multiprocessors and Thread-Level Parallelism"17h40m System Development Tools for Embedded Systems and SOC's (paper, slides)
Óscar Rafael da Silva F. Ribeiro
Abstract. A new approach for developing high-level performance models for systems-on-a-chip (SOC's) designs is presented. In this work we study the feasability of using that approach to design RED, a novel architecture based on a standard microprocessor containing a reconfigurable datapath.
Ref. "Early analysis tools for system-on-achip design"
"RED: A Reconfigurable Datapath"
Session 5
Application Specific Processors
Chairman: António Joaquim Esteves
09h00m The new Intel Xscale Microarchitecture (paper, slides)
Nuno Ricardo Carvalho de Sousa
Abstract. In embedded systems, performance and power consumption are the most important criteria to define a good processor chip. The new Intel® Xscale™ microarchitecture, an evolution from StrongARM™ microarchitecture, combines these two features, as will be detailed in this communication. We will also see the advanced techniques used by this microarchitecture core to achieve a high level of efficiency.
Ref. "The Intel® PXA250 Applications Processor"
"StrongARM: a high-performance ARM processor"
"Power optimization and management in embedded systems"09h20m A Processor Approach to build an Artificial Neural Network (paper, slides)
Alexandre Sérgio Mano
Abstract. Artificial Neural Networks (ANNs) have followed two radically dissimilar paths: software simulation and dedicated hardware. This communication introduces the main concepts behind the ANN idea and analyses one processor specifically built as a hardware tool for creating a Neural Network, capable of replicating the human's brain operations. It also tries to assess its current possibilities within the industrial framework and possible future applications.
Ref. "A PARALLEL NEURAL PROCESSOR FOR REAL-TIME APPLICATIONS"
"ULSI ARCHITECTURES FOR ARTIFICIAL NEURAL NETWORKS"09h40m TriCore: an hybrid DSP/Microcontroller Approach in the Automotive Industry (paper, slides)
Fabrice Azevedo
Abstract. Emerging applications for embedded systems require a common feature set: integration (real-time control and signal processing), persistiveness (long-term architecture, flexible, re-usable and well supported), competitiveness (performance and cost). This has driven the birth of hybrid architectures, merging RISC, DSP and uC architectures' best features, while overcoming their individual limitations. This communication lays out an analysis on the TriCore architecture, focusing on its core, innovative features and potential applications, namely those related to a specific application requirements from the automotive industry, the engine control.
Ref. "DIGITAL SIGNAL PROCESSOR TRENDS"
"Expanding Automotive Electronic Systems"
"Infineon’s TriCore Tackles DSP"
"TriCore Architecture Overview Handbook"
"32-Bit Microcontrollers TriCore"
"TriCore1 - 32-bit MCU-DSP Architecture"10h00m Mobile Processors: Future Trends (paper, slides)
Mário André Pinto Ferreira de Araújo
Abstract. Mobile devices, such as handhelds, PDA's and mobile phones, have been developing together with the need of mobility. Capabilities that go from GPS to wireless communications are making a stand in the market, and microprocessors have been adapted to each platform requirements. The aim of this communication is to present an overview of the current mobile architectures and its future trends.
Ref. "Mobile Processors Begin to Grow Up"
"Processors for Mobile Applications"
"Itsy: Stretching the Bounds of Mobile Computing"
10h20m Coffee break
Session 6
Parallel and Distributed Environments
Chairman: Luís Paulo Santos
10h50m Interconnection Technologies in High-Performance Clustering (sorry, no communication)
Arnaldo Afonso da Costa
Abstract. This communication analyses the interconnection technology impact on high-performance clusters, with a brief evaluation of current technologies. It further details a particular interconnection network - Quadric - with some application examples.
Ref. "THE QUADRICS NETWORK: HIGH-PERFORMANCE CLUSTERING TECHNOLOGY"
"Performance Evaluation of the Quadrics Interconnection Network"11h10m High Speed I/O Server Computing with InfiniBand (paper, slides)
José Luís Miranda Gonçalves
Abstract. High speed server computing heavily relies on low latency and high bandwidth interconnection technologies and fast I/O channels at each node. InfiniBand Architecture is one of the emerging technologies in this area. A brief analysis of the architecture key features is presented. Concurrent approaches and technologies are mentioned.
Ref. "Hot Interconnects"
"High-Performance Interconnects in Cluster Environments"
"New I/O Technologies Seek to End Bottlenecks"
"Aspects of the InfiniBand™ Architecture"
"InfiniBand Architecture: A Tutorial"
"Aspects of the Infiniband Architecture" (slides)
"Analysis of an Infiniband Channel Adapter"11h30m Challenges of Run-Time Load Distribution in Heterogeneous Shared Clusters (paper, slides)
Alfrânio Tavares Correia Júnior
Abstract. The aim of this paper is to show the challenges of run-time load distribution in heterogeneous shared clusters. The main feature to be analysed is the application level scheduler in parallel computing and its performance. The goals and constraints of a load management policy are presented, together with a taxonomy to classify the different types of load distribution, including the static ones. The communication closes with an introduction to a class of adaptative schedulers that addresses the problems of uncertainty in heterogeneous shared clusters.
Ref. "CASCH: A Tool for Computer-Aided Scheduling"11h50m Web Caching: a Memory-based Archictecture (paper, slides)
David Manuel Rodrigues Sora
Abstract. Caching also applies to Internet content by distributing it to multiple servers that are periodically refreshed. Performance gains can be obtained of two orders of magnitude between the original process-based Web servers and todays threaded servers. AFPA (Adaptive Fast Path Architecture - a software architecture) dramatically increase Web and other network servers capacity by caching static content in RAM, and serving that content as efficiently as possible from the kernel.
Ref. "A Web Caching Primer"
"A Survey of Web Caching Schemes for the Internet"
"The Advantages of Intel® Itanium™ Architecture for Cache Server Software"
"Adaptive Fast Path Architecture"12h10m NAS and SAN Scaling Together: a NASD Approach (paper, slides)
Luís Manuel Oliveira Soares
Abstract.This communication exhibits the state of the art of an hybrid architecture based on the merge of NAS (file oriented) and SAN (block oriented) approaches, focusing an emergent solution, the NASD architecture.
Ref. "Scalable Networked Storage: Convergence of SAN & NAS with HighRoad"
"NASD Scalable Storage Systems"
"Active Disk File System : A Distributed, Scalable File System"12h30m E-learning Cluster Computer: a Self-Learning Approach with e-Contents (paper, slides)
Hélio Manuel Vilas
Abstract. This communication stresses some relevant features on interactive Internet services on distance learning, and presents an e-learning course on "Cluster Computers" as a case study, with an in-depth analysis of its contents.
Ref. "A Crystal Ball Look Into the Future of Technology in Education"
"Cluster Computing in the Classroom: Topics, Guidelines, and Experiences"
"High Performance Cluster Computing: Architectures and Systems, Volume 1, Ch.1"
"MIT OpenCourseWare | Electrical Engineering and Computer Science"
"Online Degrees in Computer Engineering, Software Engineering & Computer Science"
12h50m Closing Session
A PG course in a fast moving technological domain usually accepts applications from students with considerably different backgrounds. To lecture Computer Architecture (CA) in an M. Sc. in Informatics, under these conditions, places a real challenge: how to seduce students with no previous knowledge in CA, and simultaneously motivate those with a solid and updated background. The obvious solution is to customize its contents to each student; but is it feasible for over 20 students, with only one lecturer who already shares his lecturing activities with other academic duties?
The ICCA approach attempts to complement the traditional set of academic lectures - which gives an updated overview of the more relevant topics in CA - with the individual commitment of each student to further explore a particular interest area in CA. ICCA plays with words (Internal is very close to International...) to encourage this new breed of scientists to organize their literature search, to filter the relevant material out of so many available sources, to structure their minds to produce a coherent message to communicate to the fellow "scientists", to practice the basic rules of science report writing (and to follow the author's instructions based on the well known "Lecture Notes on ..."), and to overcome the fear of a public talk.
This is the 4th year where this integrated approach is being applied in CA; this is also the 4th time I have to write this "Editor's Message", and 1st really re-write... Come and visit also ICCA'2002! As the organizer of this event, I proudly state that I am very pleased once again with the enthusiasm the students showed to produce, high quality communications, within tight schedules. Each student will receive a printed copy of the proceedings on the presentation day, and, for the first time, the event is 2-day long and includes a free lunch! The whole content of ICCA'03 is available in http://gec.di.uminho.pt/discip/minf/ac0203/icca03.htm.
My sincere congratulations and many thanks to all who contributed once more to make this event a successful one, namely all the M. Sc. students and my colleagues who played the role of external referees and session chairmen (António Joaquim Esteves, António Manuel Pina, João Luís Sobral, João Miguel Fernandes e Luís Paulo Santos).
Alberto José Proença
PS. A printed version of the whole set of communications, binded as a Conference Proceedings book, was a gift to all the participants in this event, at the beginning of the oral presentations. However, if anyone wishes an extra copy, is free to download and printout the communications (referenced above), plus the front cover, the table of contents and the session separators (here, in PDF). After the oral presentations, a copy of the slides shown during the talks was placed in this site (also in PDF, next to the papers, above).
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